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| rev 6.0 1 pd-97508 ir3832wmpbf features ? wide input voltage range 1.0v to 16v ? wide output voltage range 0.6v to 0.9*vin ? continuous 4a load capability ? integrated bootstrap-diode ? high bandwidth e/a for excellent transient performance ? programmable switching frequency up to 1.5 mhz ? programmable over current protection ? pgood output ? hiccup current limit ? programmable soft-start ? enable input with voltage monitoring capability ? enhanced pre-bias start-up ? vp input for ddr tracking applications ? -40 o c to 125 o c operating junction temperature ? thermal protection ? 5mm x 6mm power qfn package, 0.9 mm height ? halogen free, lead free and rohs compliant applications ? server applications ? storage applications ? embedded telecom systems fig. 1. typical application diagram highly efficient integrated synchronous buck regulato r for ddr applications sup ir buck tm boot vcc fb comp gnd pgnd sw ocset ss/ sd 4.5v rev 6.0 3 pd-97508 ir3832wmpbf block diagram fig. 2. simplified block diagram of the ir3832w rev 6.0 4 pd-97508 ir3832wmpbf pin description pin name description 1 vp track pin. use external resistors from vddq rail. the vp voltage can be set to 0.9v for ddr2 application and 0.75 or 0.6v for ddr3 application. 2 fb inverting input to the error amplifier. this pin is connected directly to the output of the regulator via resistor divider to set the output voltage and provide feedback to the error amplifier. 3 comp output of error amplifier. an external resistor and capacitor network is typically connected from this pin to fb pin to provide loop compensation. 4 gnd signal ground for internal reference and control circuitry. 5 rt set the switching frequency. connect an external resistor from this pin to gnd to set the switching frequency. 6 ss/sd soft start / shutdown. this pin provides user programmable soft-start function. connect an external capacitor from this pin to gnd to set the start up time of the output voltage. the converter can be shutdown by pulling this pin below 0.3v. 7 ocset current limit set point. a resistor from this pin to sw pin will set the current limit threshold. 8 pgood power good status pin. output is open drain. connect a pull up resistor from this pin to vcc. if unused, it can be left open. 9 v cc this pin powers the internal ic and drivers. a minimum of 1uf high frequency capacitor must be connected from this pin to the power ground (pgnd). 10 pgnd power ground. this pin serves as a separated ground for the mosfet drivers and should be connected to the system?s power ground plane. 11 sw switch node. this pin is connected to the output inductor. 12 v in input voltage connection pin. 13 boot supply voltage for high side driver. connect a 0.1uf capacitor from this pin to sw. 14 enable enable pin to turn on and off the device. 15 gnd signal ground for internal reference and control circuitry. rev 6.0 5 pd-97508 ir3832wmpbf recommended operating conditions parameter symbol test condition min typ max units power loss power loss p loss vcc=5v, v in =12v, v o =0.75v, i o =4a, fs=400khz, l=1.5uh, note4 0.51 w mosfet r ds(on) top switch r ds(on)_top v boot -v sw =5v, i d =10a, tj= 25 o c 22.6 29 bottom switch r ds(on)_bot v cc =5v, i d =10a, tj= 25 o c 15.1 20 m supply current v cc supply current (standby) i cc(standby) ss=0v, no switching, enable low 500 a v cc supply current (dyn) i cc(dyn) ss=3v, vcc=5v, fs=500khz enable high 10 ma under voltage lockout v cc -start-threshold v cc _uvlo_start vcc rising trip level 3.95 4.15 4.35 v cc -stop-threshold v cc _uvlo_stop vcc falling trip level 3.65 3.85 4.05 enable-start-threshold enable_uvlo_start supply ramping up 1.14 1.2 1.36 enable-stop-threshold enable_uvlo_stop supply ramping down 0.9 1.0 1.06 v enable leakage current ien enable=3.3v 15 a electrical specifications unless otherwise specified, these specification apply over 4.5v< v cc <5.5v, vp=0.6v, v in =12v, 0 o c rev 6.0 9 pd-97508 ir3832wmpbf rdson of mosfets over temperature at vcc=5v 12 14 16 18 20 22 24 26 28 30 -40-20 0 20406080100120140 temperature [c] resistance [m ] sync-fet ctrl-fet rev 6.0 10 pd-97508 ir3832wmpbf typical efficiency and power loss curves vin=12v, vcc=5v, vo=0.75v, io=0.5a-4a, f s =400khz, l=1.5uh (mpo104-1r5 from delta), room temperature, no air flow 81 82 83 84 85 86 87 88 89 0.51.01.52.02.53.03.54.0 load current (a) efficiency (%) 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.55 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 load current (a) power loss (w) rev 6.0 11 pd-97508 ir3832wmpbf typical efficiency and power loss curves vin=5v, vcc=5v, vo=0.75v, io=0.5a-4a, f s =400khz, l=1.5uh (mpo104-1r5 from delta), room temperature, no air flow 84 85 86 87 88 89 90 0.51.01.52.02.53.03.54.0 load current (a) efficiency (%) 0.05 0.10 0.15 0.20 0.25 0.30 0.35 0.40 0.45 0.50 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 load current (a) power loss (w) rev 6.0 12 pd-97508 ir3832wmpbf circuit description theory of operation introduction the ir3832w uses a pwm voltage mode control scheme with external compensation to provide good noise immunity and maximum flexibility in selecting inductor values and capacitor types. the switching frequency is programmable from 250khz to 1.5mhz and provides the capability of optimizing the design in terms of size and performance. ir3832w provides precisely regulated output voltage programmed via two external resistors from 0.7v to 0.9*vin. the ir3832w operates with an external bias supply from 4.5v to 5.5v, allowing an extended operating input voltage range from 1.0v to 16v. the device utilizes the on-resistance of the low side mosfet as current sense element, this method enhances the converter?s efficiency and reduces cost by eliminating the need for external current sense resistor . ir3832w includes two low r ds(on) mosfets using ir?s hexfet technology. these are specifically designed for high efficiency applications. under-voltage lockout and por the under-voltage lockout circuit monitors the input supply vcc and the enable input. it assures that the mosfet driver outputs remain in the off state whenever either of these two signals drop below the set thresholds. normal operation resumes once vcc and enable rise above their thresholds. the por (power on ready) signal is generated when all these signals reach the valid logic level (see system block diagram). when the por is asserted the soft start sequence starts (see soft start section). enable the enable features another level of flexibility for start up. the enable has precise threshold which is internally monitored by under-voltage lockout (uvlo) circuit. therefore, the ir3832w will turn on only when the voltage at the enable pin exceeds this threshold, typically, 1.2v. if the input to the enable pin is derived from the bus voltage by a suitably programmed resistive divider, it can be ensured that the ir3832w does not turn on until the bus voltage reaches the desired level. only after the bus voltage reaches or exceeds this level will the voltage at enable pin exceed its threshold, thus enabling the ir3832w. therefore, in addition to being a logic input pin to enable the ir3832w, the enable feature, with its precise threshold, also allows the user to implement an under-voltage lockout for the bus voltage v in . this is desirable particularly for high output voltage applications, where we might want the ir3832w to be disabled at least until v in exceeds the desired output voltage level. figure 3b. shows the recommended start-up sequence for the non-tracking operation of ir3832w, when enable is used as a logic input. fig. 3a. normal start up, device turns on when the bus voltage reaches 10.2v fig. 3b. recommended startup sequence, non-tracking operation rev 6.0 13 pd-97508 ir3832wmpbf soft-start the ir3832w has a programmable soft-start to control the output voltage rise and limit the current surge at the start-up. to ensure correct start-up, the soft-start sequence initiates when the enable and vcc rise above their uvlo thresholds and generate the power on ready (por) signal. the internal current source (typically 20ua) charges the external capacitor c ss linearly from 0v to 3v. figure 6 shows the waveforms during the soft start. the start up time can be estimated by: during the soft start the ocp is enabled to protect the device for any short circuit and over current condition. pre-bias startup ir3832w is able to start up into pre-charged output, which prevents oscillation and disturbances of the output voltage. the output starts in asynchronous fashion and keeps the synchronous mosfet off until the first gate signal for control mosfet is generated. figure 4 shows a typical pre-bias condition at start up. the synchronous mosfet always starts with a narrow pulse width and gradually increases its duty cycle with a step of 25%, 50%, 75% and 100% until it reaches the steady state value. the number of these startup pulses for the synchronous mosfet is internally programmed. figure 5 shows a series of 32, 16, 8 startup pulses. fig. 5. pre-bias startup pulses fig. 6. theoretical operation waveforms during soft-start (1) - - - - - - - - - - - - - - - - - - - - a 20 * ss p start c v t = fig. 4. pre-bias startup fig. 3c. recommended startup sequence, sequenced operation figure 3c. shows the recommended startup sequence for tracking operation of ir3832w with enable used as logic input. rev 6.0 14 pd-97508 ir3832wmpbf an internal current source sources current ( i ocset ) out of the ocset pin. this current is a function of the switching frequency and hence, of r t . shutdown the ir3832w can be shutdown by pulling the enable pin below its 1 v threshold. this will tri- state both, the high side driver as well as the low side driver. alternatively, the output can be shutdown by pulling the soft-start pin below 0.3v. normal operation is resumed by cycling the voltage at the soft start pin. over-current protection the over current protection is performed by sensing current through the r ds(on) of low side mosfet. this method enhances the converter?s efficiency and reduces cost by eliminating a current sense resistor. as shown in figure 7, an external resistor (r ocset ) is connected between ocset pin and the switch node (sw) which sets the current limit set point. table 1. shows i ocset at different switching frequencies. the internal current source develops a voltage across r ocset . when the low side mosfet is turned on, the inductor current flows through the q2 and results in a voltage at ocset which is given by: an over current is detected if the ocset pin goes below ground. hence, at the current limit threshold, v ocset =0. then, for a current limit setting i limit ,r ocset is calculated as follows: operating frequency the switching frequency can be programmed between 250khz ? 1500khz by connecting an external resistor from r t pin to gnd. table 1 tabulates the oscillator frequency versus r t . fig. 7. connection of over current sensing resistor an overcurrent detection trips the ocp comparator, latches ocp signal and cycles the soft start function in hiccup mode. the hiccup is performed by shorting the soft-start capacitor to ground and counting the number of switching cycles. the soft start pin is held low until 4096 cycles have been completed. the ocp signal resets and the converter recovers. after every soft start cycle, the converter stays in this mode until the overload or short circuit is removed. i ) r r i v l (on ds ocset ocset ocset .(3) .......... ) ( ) ( ? ? ? = i i r r ocset limit on ds ocset (4) .... .......... .......... ) ( * = ) 2 .....( .......... .......... .......... ) (k ) a ( = t ocset r i 1400 table 1. switching frequency and i ocset vs. external resistor ( r t ) the ocp circuit starts sampling current typically 160 ns after the low gate drive rises to about 3v. this delay functions to filter out switching noise. 143.4 1400 9.76 150.3 1500 9.31 110.2 1100 12.7 121.7 1200 11.5 130.8 1300 10.7 97.9 1000 14.3 88.6 900 15.8 78.6 800 17.8 68.2 700 20.5 59.07 600 23.7 48.7 500 28.7 39.2 400 35.7 29.4 300 47.5 i ocset ( a) f s (khz) r t (k ? ) 143.4 1400 9.76 150.3 1500 9.31 110.2 1100 12.7 121.7 1200 11.5 130.8 1300 10.7 97.9 1000 14.3 88.6 900 15.8 78.6 800 17.8 68.2 700 20.5 59.07 600 23.7 48.7 500 28.7 39.2 400 35.7 29.4 300 47.5 i ocset ( a) f s (khz) r t (k ? ) rev 6.0 15 pd-97508 ir3832wmpbf power good output the ic continually monitors the output voltage via feedback (fb pin). the power good signal is flagged when the fb pin voltage is above 0.5v and between 85% to 115 % of vp. this pin is open drain and it needs to be externally pulled high. high state indicates that output is in regulation. fig. 8a shows the pgood timing diagram for non-tracking operation. in this case, during startup, pgood goes high after the ss voltage reaches 2.1v if the fb voltage is within the pgood comparator window. fig. 8a. and fig 8b. also show a 256 cycle delay between the fb voltage entering within the thresholds defined by the pgood window and pgood going high. thermal shutdown temperature sensing is provided inside ir3832w. the trip threshold is typically set to 140 o c. when trip threshold is exceeded, thermal shutdown turns off both mosfets and discharges the soft start capacitor. automatic restart is initiated when the sensed temperature drops within the operating range. there is a 20 o c hysteresis in the thermal shutdown threshold. fig.4a ir3832w non-tracking operation timing diagram of pgood function fig.8b ir3832w tracking operation rev 6.0 16 pd-97508 ir3832wmpbf minimum on time considerations the minimum on time is the shortest amount of time for which the control fet may be reliably turned on, and this depends on the internal timing delays. for the ir3832w, the typical minimum on-time is specified as 50 ns. any design or application using the ir3832w must ensure operation with a pulse width that is higher than this minimum on-time and preferably higher than 100 ns. this is necessary for the circuit to operate without jitter and pulse- skipping, which can cause high inductor current ripple and high output voltage ripple. in any application that uses the ir3832w, the following condition must be satisfied: the minimum output voltage for the ir3832w is limited to v out(min) = 0.6 v. furthermore, for the ir3832w, especially for active bus termination applications, it is strongly recommended to use a switching frequency of 400 khz to obtain clean and jitter free operation in sourcing as well as sinking modes. therefore, the maximum input voltage that may be stepped down to 0.6v at 400 khz without jitter or pulse skipping is 15 v. v/s 6 ns 100 v 0.6 v v in (min) (min) in 6 10 = s on out s f t v f maximum duty ratio considerations a fixed off-time of 200 ns maximum is specified for the ir3832w. this provides an upper limit on the operating duty ratio at any given switching frequency. it is clear, that higher the switching frequency, the lower is the maximum duty ratio at which the ir3832w can operate. to allow a margin of 50ns, the maximum operating duty ratio in any application using the ir3832w should still accommodate about 250 ns off-time. fig 9. shows a plot of the maximum duty ratio v/s the switching frequency, with 250 ns off-time. s out s on f v f d t v in = = (min) (min) (min) on out s in s in out on on on t v f v f v v t t t fig. 9. maximum duty cycle v/s switching frequency. max duty cycle 55 60 65 70 75 80 85 90 95 250 450 650 850 1050 1250 1450 1650 switching frequency (khz) max duty cycle (%) rev 6.0 17 pd-97508 ir3832wmpbf ir3832w v in when an external resistor divider is connected to the output as shown in figure 10. equation (5) can be rewritten as: for low voltage applications, such as this design, it is often advisable to eliminate the bias resistor r9 from fb to ground. for the calculated value of r8 see feedback compensation section. further, the tracking reference vp may be itself derived from some master reference by means of a resistive divider as shown in fig. 9. this is common in active bus termination circuits such as voltage tracking termination (vtt) where the tracking reference vp may be obtained as half of the master reference vddq which forms the input to one or more memory banks. in this design, vddq =1.5v r p1 = r p2 =1.5 k ? vp =0.75v soft-start programming the soft-start timing can be programmed by selecting the soft-start capacitance value. from (1), for a desired start-up time of the converter, the soft start capacitor can be calculated by using: where t start is the desired start-up time (ms). for tracking applications the output is generally required to track vp even at start-up. hence, it is necessary to ensure that the ss pin is already up to 3 v before the tracking reference signal is applied to the vp pin. this can be done by choosing a small value for the soft-start capacitor to ensure that the voltage at the ss pin rises to 3 v quickly. a 0.022 uf capacitor is chosen for this purpose. application information design example: the following example is a typical application for ir3832w. the application circuit is shown on page 23. enabling the ir3832w as explained earlier, the precise threshold of the enable lends itself well to implementation of a uvlo for the bus voltage. for a typical enable threshold of v en = 1.2 v for a v in (min) =10.2v, r 1 =49.9k and r 2 =7.50k is a good choice. programming the frequency for f s = 400 khz, select r t = 35.7 k ? , using table. 1. output voltage programming output voltage is programmed by the tracking reference voltage at vp and external voltage divider. the divider is ratioed such that the voltage at the fb pin is equal to the voltage at the vp pin pin when the output is at its desired value. the output voltage is defined by using the following equation: khz 400 = f 22.5mv v a 4 = i v 0.75 = v max) 13.2v ( v 12 = v s o o o in .....(7) .......... .......... .......... ? ? ? ? ? ? ? ? + ? = 9 8 1 r r v v p o fig. 10. typical application of the ir3832w for programming the output voltage (8) .... .......... .......... .......... v v v r r p o p ? ? ? ? ? ? ? ? ? ? = 8 9 t c start ss (9) .......... 0.02857 ) ms ( ) f ( = enable r 2 r 1 v r r r v en in (5) .......... 1.2 * (min) = = + 2 1 2 v v v r r en ) in( en (6) .......... min ? = 1 2 rev 6.0 18 pd-97508 ir3832wmpbf where: d is the duty cycle i rms is the rms value of the input capacitor current. i o is the output current. for i o =4 a and d = 0.0625, the i rms = 0.97 a ceramic capacitors are recommended due to their peak current capabilities. they also feature low esr and esl at higher frequency which enables better efficiency. for this application, it is advisable to have 2x10uf 16v ceramic capacitors ecj-3yb1c106m from panasonic. in addition to these, although not mandatory, a 330uf 25v smd capacitor eev-fk1e 332p from panasonic may be used as a bulk capacitor, and is recommended if the input power supply is not located close to the converter. inductor selection the inductor is selected based on output power, operating frequency and efficiency requirements. a low inductor value results in a smaller size and faster response to a load transient but poor efficiency and high output noise due to large ripple current. generally, the selection of the inductor value can be reduced to the desired maximum ripple current in the inductor . the optimum point is usually found between 20% and 50% ripple of the output current. for the buck converter, the inductor value for the desired operating ripple current can be determined using the following relation: where: if i 30%( i o ), then the output inductor is calculated to be 1.46 h. select l =1.50 h. the mpo104-1r5 from delta provides a compact, low profile inductor suitable for this application. bootstrap capacitor selection to drive the control fet, it is necessary to supply a gate voltage at least 4v greater than the voltage at the sw pin, which is connected the source of the control fet . this is achieved by using a bootstrap configuration, which comprises the internal bootstrap diode and an external bootstrap capacitor (c6), as shown in fig. 11.. the operation of the circuit is as follows: when the lower mosfet is turned on, the capacitor node connected to sw is pulled down to ground. the capacitor charges towards v cc through the internal bootstrap diode, which has a forward voltage drop v d . the voltage v c across the bootstrap capacitor c6 is approximately given as when the upper mosfet turns on in the next cycle, the capacitor node connected to sw rises to the bus voltage v in . however, if the value of c6 is appropriately chosen, the voltage v c across c6 remains approximately unchanged and the voltage at the boot pin becomes a bootstrap capacitor of value 0.1uf is suitable for most applications. input capacitor selection the ripple current generated during the on time of the upper mosfet should be provided by the input capacitor. the rms value of this ripple is expressed by: ....(12) .......... .......... ) ( d d i i o rms ? ? ? = 1 (13) .. .......... .......... .......... in o v v d = ) ( i cycle duty time on turn frequency switching current ripple inductor voltage output voltag e input maximum = = = = = = d t f i v v s o in () (14) ... .......... .......... * ; s in o o in s o in f i v v v v l f d t t i l v v ? ? ? = ? = ? = ? 1 fig. 11. bootstrap circuit to generate vc voltage (11) .......... .......... .......... .......... d cc in boot v v v v ? + ? (10) .......... .......... .......... .......... d cc c v v v ? ? rev 6.0 19 pd-97508 ir3832wmpbf (15) ..... .......... .......... current ripple inductor i ripple voltage output v f * c * i v esl * l v v v esr * i v v v v v l o s o l ) c ( o o in ) esl ( o l ) esr ( o ) c ( o ) esl ( o ) esr ( o o = = = ? ? ? ? ? ? ? = = + + = 8 since the output capacitor has a major role in the overall performance of the converter and determines the result of transient response, selection of the capacitor is critical. the ir3832w can perform well with all types of capacitors. as a rule, the capacitor must have low enough esr to meet output ripple and load transient requirements. the goal for this design is to meet the voltage ripple requirement in the smallest possible capacitor size. therefore it is advisable to select ceramic capacitors due to their low esr and esl and small size. six of the panasonic ecj- 2fb0j226ml (22uf, 6.3v, 3mohm) capacitors is a good choice. feedback compensation the ir3832w is a voltage mode controller. the control loop is a single voltage feedback path including error amplifier and error comparator. to achieve fast transient response and accurate output regulation, a compensation circuit is necessary. the goal of the compensation network is to provide a closed-loop transfer function with the highest 0 db crossing frequency and adequate phase margin (greater than 45 o ). the output lc filter introduces a double pole, ?40db/decade gain slope above its corner resonant frequency, and a total phase lag of 180 o (see figure 12). the resonant frequency of the lc filter is expressed as follows: figure 12 shows gain and phase of the lc filter. since we already have 180 o phase shift from the output filter alone, the system runs the risk of being unstable. the ir3832w uses a voltage-type error amplifier with high-gain (110db) and wide-bandwidth. the output of the error amplifier is available for dc gain control and ac phase compensation. the error amplifier can be compensated either in type ii or type iii compensation. local feedback with type ii compensation is shown in fig. 13. this method requires that the output capacitor should have enough esr to satisfy stability requirements. in general the output capacitor?s esr generates a zero typically at 5khz to 50khz which is essential for an acceptable phase margin. the esr zero of the output capacitor is expressed as follows: (16) .. .......... .......... .......... o o lc c l f ? ? = 2 1 fig. 12. gain and phase of lc filter (17) ....... .......... .......... o esr *esr*c f ? = 2 1 output capacitor selection the voltage ripple and transient requirements determine the output capacitors type and values. the criteria is normally based on the value of the effective series resistance (esr). however the : actual capacitance value and the equivalent series inductance (esl) are other contributing components. these components can be described as phase 0 0 f lc -180 0 frequency gain f lc 0 db frequency -40db/decade rev 6.0 20 pd-97508 ir3832wmpbf the transfer function ( v e /v o ) is given by: the (s) indicates that the transfer function varies as a function of frequency. this configuration introduces a gain and zero, expressed by: first select the desired zero-crossover frequency ( f o ): use the following equation to calculate r3: v out v ref r 9 r 8 c pole c 4 r 3 ve f z f pole e/a z f frequency gain(db) h(s) db fb comp z in fig. 13. type ii compensation network and its asymptotic gain plot (18) ..... ) ( 4 8 4 3 1 c sr c sr z z s h v v in f o e + ? = ? = = () (20) ........ .......... .......... * * (19) ......... .......... .......... ......... 4 3 8 3 2 1 c r f r r s h z = = () s esr o f f f * 1/10 ~ 1/5 f and o > (21) ....... .......... .......... * * * * 2 8 3 lc in esr o osc f v r f f v r = where: v in = maximum input voltage v osc = oscillator ramp voltage f o = crossover frequency f esr = zero frequency of the output capacitor f lc = resonant frequency of the output filter r 8 = feedback resistor to cancel one of the lc filter poles, place the zero before the lc filter resonant frequency pole: use equations (20), (21) and (22) to calculate c4. one more capacitor is sometimes added in parallel with c4 and r3. this introduces one more pole which is mainly used to suppress the switching noise. the additional pole is given by: the pole sets to one half of the switching frequency which results in the capacitor c pole : for a general solution for unconditional stability for any type of output capacitors, and a wide range of esr values, we should implement local feedback with a type iii compensation network. the typically used compensation network for voltage-mode controller is shown in figure 14. again, the transfer function is given by: by replacing z in and z f according to figure 14, the transfer function can be expressed as: (22) ....... .......... .......... .......... * * . % o o z lc z c l f f f 2 1 75 0 75 = = ...(23) .......... .......... .......... * * * pole pole p c c c c r f + = 4 4 3 2 1 (24) 1 1 1 3 4 3 .. .......... .......... *f *r c *f *r c s s pole ? ? = in f o e z z s h v v ? = = ) ( () [ ] (25) .... ) ( * ) ( ) ( ) ( 7 10 3 4 3 4 3 3 4 8 10 8 7 4 3 1 1 1 1 c sr c c c c sr c c sr r r sc c sr s h + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + + + + + + ? = rev 6.0 21 pd-97508 ir3832wmpbf tantalum ceramic f lc rev 6.0 23 pd-97508 ir3832wmpbf application diagram: fig. 15. application circuit diagram for a 12v to 0.75 v, 4 a point of load converter suggested bill of materials for the application circuit: part reference quantity value description manufacturer part number 1 330uf smd elecrolytic, fsize, 25v, 20% panasonic eev-fk1e331p 2 10uf 1206, 16v, x5r, 20% tdk c3216x5r1e106m 1 0.1uf 0603, 25v, x7r, 10% panasonic ecj-1vb1e104k lo 1 1.5uh 11.5x10x4mm, 20%, 1.7mohm delta mpo104-1r5 co 6 22uf 0805, 6.3v, x5r, 20% panasonic ecj-2fb0j226ml r1 1 49.9k thick film, 0603,1/10 w,1% rohm mcr03ezpfx4992 r2 1 7.5k thick film, 0603,1/10w,1% rohm mcr03ezpfx7501 r t 1 35.7k thick film, 0603,1/10w,1% rohm mcr03ezpfx3572 r ocset 1 2.74k thick film, 0603,1/10w,1% rohm mcr03ezpfx2741 r pg 1 10k thick film, 0603,1/10w,1% rohm mcr03ezpfx1002 c ss 1 0.022uf 0603, 25v, x7r, 10% panasonic ecj-1vb1e223k r3 1 3.48k thick film, 0603,1/10w,1% rohm mcr03ezpfx3481 c3 1 220pf 50v, 0603, npo, 5% panasonic ECJ-1VC1H221J c6 1 0.1uf 0603, 25v, x7r, 10% panasonic ecj-1vb1e104k c4 1 2200pf 0603, 50v, x7r, 10% panasonic ecj-1vb1h223k r8 1 6.65k thick film, 0603,1/10w,1% rohm mcr03ezpfx6651 r10 1 210 thick film, 0603,1/10w,1% rohm erj-3ekf2100v c7 1 2200pf 0603, 50v, x7r, 10% panasonic ecj-1vb1h222k c p2 1 10nf 0603, 50v, x7r, 10% panasonic ecj-1vb1h103k c vcc 1 1.0uf 0603, 16v, x5r, 20% panasonic ecj-bvb1c105m u1 1 ir3832w supirbuck, 4a, pqfn 5x6mm international rectifier ir3832wmpbf cin rev 6.0 24 pd-97508 ir3832wmpbf typical operating waveforms vin=12.0v, vcc=5v, vo=0.75v, io=0- 4a, room temperature, no air flow fig. 20: output voltage ripple, 4a, sourcing current, ch 2 : v out fig. 18: inductor node at 4a, sourcing current, ch 3 :sw, ch 4 :i out fig. 21: short (hiccup) recovery ch 2 :v out , ch 3 :v ss , ch 4 :pgood fig. 16: start up at 4a, sourcing current ch 1 :pgood, ch 2 :v out , ch 3 :v ddq , ch 4 :ss fig. 19: inductor node at -3a, sinking current, ch 3 :sw , ch 4 :i out fig. 17: start up with prebias, 0a load ch 1 :pgood, ch 2 :v out ,ch 3 :v ddq, ch 4 :ss rev 6.0 25 pd-97508 ir3832wmpbf typical operating waveforms vin=12v, vcc=5v, vo=0.75v, room temperature, no air flow fig. 24: transient response, 1a/us -0.5a to +0.5a load , ch 2 :v out , ch 4 :i o fig. 23: tracking -3a load, sinking current, ch 2 :v out , ch 3 :v ddq , ch 4 :pgood fig. 22: tracking 4a, sourcing current, ch 2 :v out , ch 3 :v ddq , ch 4 :pgood rev 6.0 26 pd-97508 ir3832wmpbf typical operating waveforms vin=12v, vcc=5v, vo=0.75v, io=+4a, room temperature, no air flow fig.25: bode plot at 4a load (sourcing current ) shows a bandwidth of 65khz and phase margin of 60 degrees rev 6.0 27 pd-97508 ir3832wmpbf layout considerations the layout is very important when designing high frequency switching converters. layout will affect noise pickup and can cause a good design to perform with less than expected results. make all the connections for the power components in the top layer with wide, copper filled areas or polygons. in general, it is desirable to make proper use of power planes and polygons for power distribution and heat dissipation. the inductor, output capacitors and the ir3832w should be as close to each other as possible. this helps to reduce the emi radiated by the power traces due to the high switching currents through them. place the input capacitor directly at the vin pin of ir3832w. the feedback part of the system should be kept away from the inductor and other noise sources. the critical bypass components such as capacitors for vcc should be close to their respective pins. it is important to place the feedback components including feedback resistors and compensation components close to fb and comp pins. pgnd vin agnd vout pgnd vin agnd vout the connection between the ocset resistor and the sw pin should not share any trace with the connection between the bootstrap capacitor and the sw pin. instead, it is recommended to use a kelvin connection of the trace from the ocset resistor and the trace from the bootstrap capacitor at the sw pin. in a multilayer pcb use one layer as a power ground plane and have a control circuit ground (analog ground), to which all signals are referenced. the goal is to localize the high current path to a separate loop that does not interfere with the more sensitive analog control function. these two grounds must be connected together on the pc board layout at a single point. the power qfn is a thermally enhanced package. based on thermal performance it is recommended to use at least a 4-layers pcb. to effectively remove heat from the device the exposed pad should be connected to the ground plane using vias. figure 26 illustrates the implementation of the layout guidelines outlined above, on a 4 layer board. pgnd vin agnd vout all bypass caps should be placed as close as possible to their connecting pins. resistors rt and rocset should be placed as close as possible to their pins. enough copper & minimum length ground path between input and output pgnd vin agnd compensation parts should be placed as close as possible to the comp pin . fig. 26a. ir3832w layout considerations ? top layer vout rev 6.0 28 pd-97508 ir3832wmpbf pgnd vin agnd power ground plane analog ground plane single point connection between agnd & pgnd, should be close to the supirbuck, kept away from noise sources. use separate traces for connecting boot cap and rocset to the switch node and with the minimum length traces. avoid big loops. fig. 26c. ir3832w layout considerations ? mid layer 1 fig. 26d. ir3832w layout considerations ? mid layer 2 feedback trace should be kept away form noise sources fig. 26b. ir3832w layout considerations ? bottom layer rev 6.0 29 pd-97508 ir3832wmpbf pcb metal and components placement lead lands (the 11 ic pins) width should be equal to nominal part lead width. the minimum lead to lead spacing should be 0.2mm to minimize shorting. lead land length should be equal to maximum part lead length + 0.3 mm outboard extension. the outboard extension ensures a large and inspectable toe fillet. pad lands (the 4 big pads other than the 11 ic pins) length and width should be equal to maximum part pad length and width. however, the minimum metal to metal spacing should be no less than 0.17mm for 2 oz. copper; no less than 0.1mm for 1 oz. copper and no less than 0.23mm for 3 oz. copper. rev 6.0 30 pd-97508 ir3832wmpbf solder resist it is recommended that the lead lands are non solder mask defined (nsmd). the solder resist should be pulled away from the metal lead lands by a minimum of 0.025mm to ensure nsmd pads. the land pad should be solder mask defined (smd), with a minimum overlap of the solder resist onto the copper of 0.05mm to accommodate solder resist mis-alignment. ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. rev 6.0 31 pd-97508 ir3832wmpbf stencil design ? the stencil apertures for the lead lands should be approximately 80% of the area of the lead lads. reducing the amount of solder deposited will minimize the occurrences of lead shorts. if too much solder is deposited on the center pad the part will float and the lead lands will be open. ? the maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease the incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. rev 6.0 32 pd-97508 ir3832wmpbf ir world headquarters: 233 kansas st., el segundo, california 90245, usa tel: (320) 252-7105 tac fax: (320) 252-7903 this product has been designed and qualified for the industrial market (note5) visit us at www.irf.com fo r sales contact information data and specifications subject to change without notice. 08/11 bottom view |
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